With the continuous progress in the manufacturing technology of integrated circuits (IC), the minimum size of IC chips also keeps going down. However, with this trend in the physical design of reducing chip sizes, it is more necessary to consider the impact of manufacturability on the yield and reliability. Particularly with the introduction of advanced nano-class processes, many problems in the yield and reliability may be caused by certain layout patterns, or may be known of as process hotspots or hotspots. These patterns are easily affected by the recipe of the manufacturing process, such as change in stress and lithographic process, thus causing various defects (open circuits or short circuits) in the layout. Therefore, it is necessary to be able to identify these patterns, and even to modify these patterns to help with increasing the yield.
The major cause for difficulty in increasing the yield recently is an increase by a large margin of the number of hotspots in the lithographic process, which is a problem due to complexity of the layout design, when the technology nodes are reduced to less than 65 nm. Although the problem of these lithography hotspots can be treated with resolution enhancement technology during an optical proximity correction (OPC) phase, and improvements are made by modifying the wire design at the lithography hotspots, a huge number of computer computations are required in this phase, and the changeable amplitude of the wire design is obviously inadequate, that is, lithography hotspots cannot be entirely eliminated by means of optical proximity correction. If the presence of lithography hotspots can be considered in an earlier phase of the flow process of design, this will be more helpful for enhancing the efficiency of the overall design, and for ensuring the solution of the problem of hotspots.
Generally speaking, current layout designers will try to find hotspots using a design standard provided by the wafer manufacturer, such as: the lithography rule check, and can modify the wire design at the lithography hotspot to meet the requirements of said standard. However, this method to detect and modify hotspots purely relying on the standard is very likely to lead to the incorrect detection of hotspots. The problem of incorrect detection is becoming more and more serious with an increase in the number of design standards, and especially if an IC design uses a manufacturing process below 65 nm, this problem is even more serious.
Traditional methods to correct lithography hotspots in wire layouts as mentioned above are mostly after the optical proximity correction phase, but because it takes a lot of time to adjust the recipe in the optical proximity correction process, and modifying the wire is not very elastic, therefore if the effect of optical lithography can also be considered before other earlier phases, such as: the post-routing phase, then the difficulty of traditional methods can be improved.
Currently there is a pattern-matching based method that is a correcting method after the wiring phase to correct the presence of lithography hotspots in the wire layout. Because this method uses pattern matching, it needs to set up many pattern databases. Yet actually there is no way to include all patterns that may cause lithography hotspots, and therefore only limited lithography hotspots can be identified and modified. As a result, the proportion of hotspots that are modified is too low. Furthermore, this kind of pattern database not only takes up a huge amount of storage, but also requires verification of and experiments on different patterns of various kinds, thus costing a lot of time. It is obvious that this technology of testing and modifying hotspots is similar to manual modification, and as its use is limited and correction guidance information of the design standard is not taken into consideration, many cycles of errors and corrections (trial and error) must be performed before it can bring about a slightly better result. In fact, this technology cannot attain fast and effective, high-percentage correction results of hotspots, that is, it is really difficult for the circuit designer to execute this highly manual method successfully within a limited time.
Therefore, the electronic design automation industry needs an automatic and efficient lithography hotspot correcting method, in order to solve the problems that are encountered in current circuit design.